1. Field of the Invention
The present invention relates to buffered data devices used to minimize the time dedicated by a host unit to the transfer of data between an input/output (I/O) device and the host. More particularly, the invention concerns a method and apparatus for reducing or eliminating the delay between the time the last bit of data is transferred from the host unit to the input/output (I/O) unit and the time the host unit is no longer involved in performing the data transfer function.
2. Description of the Related Art
Data processing systems are exemplified by a host processor which can manipulate, format and execute arithmetic operations on data received from an I/O unit. Tape readers, disk readers and other peripheral sources of data are generally more limited in their capacity to transfer data than the host processor and the channel connecting the host processor to the I/O unit. Speed matching buffers are typically employed to match the I/O unit data transfer rate to the channel data transfer rate.
Generally, in prior art buffer devices, an effort is made to preserve the channel data transfer rate to maximize channel utilization while serving a plurality of I/O devices. This goal can be achieved by first writing the channel data into a buffer memory at the data channel transfer rate. When the I/O unit is ready to receive the I/O unit data, the buffer memory contents are read to the I/O unit at the I/O unit transfer rate.
Such techniques, while preserving channel capacity and data transfer capabilities, degrade overall system performance. Degradation of overall system performance is common because the time required to write to the buffer memory with channel data, and then to read the memory contents, can be greater than the time required if the I/O unit were directly connected for data transfer from the data channel. This time loss accounts for the majority of time it takes to transfer data from a host system utilizing the data channel to the I/O unit.
Various attempts have been made in the past to reduce the time lost in making such a data transfer. One technique, described in U.S. Pat. No. 4,258,418, describes a buffer having a threshold which identifies the buffer memory capacity level at which the READ operation is to commence. The READ operation will begin before the WRITE operation is completed. The threshold is selected to avoid exceeding the capacity of the buffer without regard to data transfer degradation. The buffer memory is written and read such as to maintain the buffer storage level at a predetermined fraction of the total storage capacity.
In another technique, described in U.S. Pat. No. 4,860,193, a buffer is described using a different threshold which identifies a bit of the next consecutive block of data bits to be loaded in the buffer memory. When the bit is received by the buffer memory, the buffer unload cycle begins. The buffer load and unload cycles are conducted simultaneously. An optimum threshold is determined by observing the previous data transfer. The invention assumes that data transfer sizes tend to an average data transfer size in data processing applications. From examining previously received data transfers, a threshold is established which identifies an expected bit length for the next consecutive transfer of data to be loaded into memory. This method requires that previously loaded data blocks be monitored in order for the threshold to be established and updated.
For the foregoing reasons, there is a need for a method and apparatus to maximize data transfer rates based upon data currently being transferred from a data channel to an I/O unit and which minimizes degradation to overall system performance.